Field of the Invention
The present invention relates to memory devices and systems including error correction code (ECC) logic.
Description of Related Art
Memory technologies used for integrated circuit memories are being developed at smaller and smaller technology nodes, and are being deployed on larger and larger memory arrays on a single integrated circuit. As the technology for memory cells advances, the margins for sensing the data can become tighter. Also, the ability of the memory cells to hold data values in the presence of disturbance of the memory cell state caused by high speed and high volume accesses to the memory cells and to neighboring memory cells can be limited by the tighter margins.
To address issues like those that arise from tighter margins and memory cell disturbance, as these technologies scale in size and density, use of error correcting codes (ECCs) embedded with integrated circuit memory has been developed. However, each memory has limited resources for storing error correcting codes.
Thus, it is desirable to provide a method that efficiently utilizes limited resources available in a memory for ECCs.